1. Field of the Invention
The present invention relates to an inter-CPU data transfer device for a multi-CPU electronic control apparatus including a plurality of CPUs which transfer and share data thereamong.
2. Description of Related Art
It is common that a vehicle-use electronic control apparatus includes a microcomputer (referred to as CPU hereinafter) to perform various controls such as a fuel injection control of a vehicle engine, and a gear shift control of an automatic transmission. In recent years, multi-CPU electronic control apparatuses in which a plurality of CPUs cooperate to perform various control processes are being used to allow for increase of the number of control processes to be performed and increasing complexity of the control processes.
In such a multi-CPU electronic control apparatus, data has to be shared among the plurality of the CPUs. In a case where the multi-CPU electronic control apparatus includes two CPUs, as a measure to share data, it is known to provide a dual port RAM (DPRAM) which is shared by the two CPUs, as disclosed in Japanese Patent Applications laid-open No. 3-129548, and No. 5-8664. However, the provision of the DPRAM incurs increase of hardware complexity and production cost.
Another possible option for sharing data not requiring the provision of a DPRAM is adoption of a semaphore system where each of the two CPUs is configured to be able to access not only its own RAM, but also a RAM of the other CPU, and where one CPU which has failed to obtain access rights to these RAMs waits while the other CPU which has succeeded in obtaining the access rights writes data to these RAMs, and after the access rights are released, the one CPU accesses its own RAM to read data therefrom.
FIG. 7 shows an example of such a semaphore system with an arbitration mechanism adopted for a fuel injection control performed by two CPUs (CPU 1 and CPU 2). In this example, the CPU 1 performs a sensor handling function in order to convert an analog signal from a water temperature sensor detecting a cooling water temperature of a vehicle engine (may be referred to as “engine water temperature” hereinafter) into a digital signal, convert an analog signal from an intake air temperature sensor detecting an intake air temperature of the vehicle engine into a digital signal, and updates an engine water temperature data item and an intake air temperature data item by these digital signals. While, the CPU 2 performs an injection amount calculating function in order to calculate a fuel injection amount as a controlled variable referring to the cooling water temperature data item and the intake air temperature data item periodically updated by the CPU 1. For the CPU 2 to accurately calculate the fuel injection amount, all the data items (engine water temperature data item and intake air temperature data item) must be updated at the same timing. Hereinafter, a plurality of data items which are used for calculating a controlled variable, and accordingly need to be updated at the same timing are called “data items to be synchronous”.
As shown in FIG. 7, the sensor handling function performed by the CPU 1 begins by inhibiting interruption (step S11). Next the CPU 1 obtains an access right to a RAM of the CPU 2, to disable the CPU 2 from accessing the RAM of the CPU 2 (step S12).
After that, an analog signal from the water temperature sensor is converted into a digital signal, and the engine water temperature data item stored in the RAM of the CPU 1 is updated by this digital signal (step S13). Likewise, an analog signal from the intake air temperature sensor is converted into a digital signal, and the intake air temperature data item stored in the RAM of the CPU 1 is updated by this digital signal (step S14).
At step S13, 14, the engine water temperature data item and the intake air temperature data item stored in the RAM of the CPU 2 are also updated by these digital signals, so that the data items stored in the RAM of the CPU 2 are identical to those stored in the RAM of the CPU 1. Here, it is assumed that the engine water temperature data item has been updated from 80 degrees C. to 90 degrees C., and the intake air temperature data item has been updated from 20 degrees C. to 25 degrees C.
Next, the sensor handling function proceeds to step S15 to release the access right to the RAM of the CPU 2, and then proceeds to step S16 to permit interruption.
On the other hand, the injection amount calculating function performed by the CPU 2 begins by inhibiting interruption (step S21). Next, the CPU 2 tries to obtain the access right to the RAM thereof. However, since this access right has been already taken by the CPU 1, the CPU 2 continues to issue requirement of the access right until the CPU 1 releases this access right (step S22).
After the CPU 1 releases the access right to the RAM of the CPU 2, and the CPU 2 obtains this access right, the injection amount calculating function proceeds to step 23 to read the engine water temperature data item from the RAM thereof, and then proceeds to step S24 to read the intake air temperature data item from the RAM thereof. Subsequently, the fuel injection amount is calculated on the basis of these data items. The injection amount calculating function is completed by permitting interruption at step S25.
The above described semaphore system with an arbitration mechanism enables an exclusive access to the data items to be synchronous, to thereby prevent the CPU 2 from reading data items some of which have not been subjected to a most recent update, and the others of which have been subjected to the most recent update, and erroneously performing calculation on the basis of the data items updated at different timings.
Incidentally, the reason for inhibiting interruption at the first step (step S11, step 21) and permitting interruption at the last step (step S16, step S25) in the sensor handling function performed by the CPU 1 and the injection amount calculating function performed by the CPU 2 is to attain high commonality of an application program between the multi-CPU electronic control apparatus as described above and a single-CPU electronic control apparatus which includes only a single CPU, but has a capability of the exclusive access control for the data items to be synchronous.
To give an example, in the case of a single-CPU electronic control apparatus, the sensor handling function and the injection amount calculating function are performed by the same one CPU. Accordingly, if, during the progress of the sensor handling function (that is, during the progress of update of the data items to be synchronous), an interruption is accepted to start a data reference process in which a plurality of data items being updated in succession by the sensor handling function are referred to for calculation purpose (for example, the above described fuel injection amount calculation), it causes that data items having been subjected to a most recent update and data items not having been subjected to the most recent update are used in the same data reference process, as a result of which calculation is erroneously performed on the basis of these data items updated at different timings. To avoid this, the sensor handling function is designed to begin by inhibiting interruption.
Likewise, if, during the progress of a data reference process such as the injection amount calculating function, an interruption is accepted to start the sensor handling function, it also causes erroneous calculation, because the timing at which data items read before this interruption have been updated is different from the timing at which data items read after completion of the sensor handling function have been updated.
As explained above, the semaphore system with an arbitration mechanism as shown in FIG. 7 enables an exclusive access control for the data items to be synchronous. However this system has a technical challenge that the advantage of high processing speed commonly expected of a multi-CPU system having a parallel operation capability is lost, because the CPU 2 has to wait until the CPU 1 releases the access right to the RAM 2 of the CPU 2 when the CPU 2 is requested to start a data reference process such as the injection amount calculating function in which data items to be synchronous are referred to. This considerably lowers processing efficiency, especially in the case of an application program for engine control, because such an application program includes a number of calculating functions requiring data items to be synchronous.
Furthermore, in the system as shown in FIG. 7, if both the CPU 1 and the CPU 2 try to obtain the access right to the same RAM at the same time, there is a possibility that there occurs a deadlock state in which both the CPU 1 and the CPU 2 wait the release of the access right. To avoid this, it becomes necessary to pay careful attention to the order in which the CPUs obtain an access right to each RAM. However, this considerably lowers a program developing efficiency. To give an example, in a case where an existing application program developed for a single-CPU electronic control apparatus is diverted for use in a multi-CPU electronic control apparatus, it must be reviewed and altered at a number of portions thereof.